Advancing cache contention analysis

When an architect builds a skyscraper, they choose materials and designs that will best support the structure. A computer architect does the same thing when creating a central processing unit (CPU). The computer architect must analyze potential weak points before building the infrastructure to ensure that the CPU is as robust and functional as possible. This process typically includes cache contention analysis. When multiple CPU cores share the same cache resources, it causes cache contention which can degrade CPU performance and lead to errors. Cache contention analysis finds potential places where multiple CPUs could be accessing the same cache at the same time, allowing computer engineers to address these problem areas before they cause trouble.

Current methods of cache contention analysis utilize an adjacent core which does not accurately reflect the randomization of real-world contention. Additionally, performing cache contention analysis is a time- and resource-intensive process. As computers become more complex and perform increasingly in-demand services, the need for fast, accurate cache contention analysis is growing.

A team including first author and PhD candidate in electrical engineering Cesar Gomes, Associate Professor Mark Hempstead of the Department of Electrical and Computer Engineering, and Carnegie Melon PhD student and undergraduate alum Xuesi Chen, E22, recently presented a paper introducing a more efficient way to complete cache contention analysis. Their program, called Probabilistic Induction of Theft Evictions (PInTE), builds on Gomes and Hempstead’s previous work on theft evictions.

The authors say, “Real systems have resource contention, so evaluating micro-architecture techniques, cache policies or system designs in isolation alone is no longer responsible design or research practice.” PInTE allows programmers to control contention induction, which would lead to faster and more realistic cache contention analysis. It requires fewer simulations than comparable methods, thereby reducing the cost of analysis. Designed for computer architects and application/system designers during the design process or workload assessments of their projects, PInTE considerably streamlines cache contention analysis.

The team presented the paper at the 2022 Institute of Electrical and Electronics Engineers (IEEE) Symposium on Workload Characterization (IISWC) in Austin, TX, during the Microarchitecture/Hardware Performance Analysis session. The symposium aims to highlight cutting-edge research on workloads for computers in commercial, consumer, and engineering sectors. Hempstead is the head of the Tufts Computer Architecture research lab, which focuses on methods to increase energy efficiency across the boundaries of circuits, architecture, and systems.